Silicon Access Networks

Due to traffic growth and the advent of advanced transport technologies, Internet aggregate bandwidth is doubling every six months.

In addition, the Internet is being adapted to carry multiple traffic types, including not only HTTP, application sessions, mail, and file transfers, but also including delay and jitter-sensitive data such as video and voice. In addition, multicasting and enhanced security features are being introduced. These improvements require advanced capabilities, including Quality of Service, which result in a dramatic expansion in the amount of processing done on each packet.

Routers used to connect carriers to carriers, carriers to national service providers, and carriers to ISPs are the foundation of the Internet. Such routers have experienced a rapid growth in capability, and numerous companies have announced or are working on terabit routers, e.g. systems that provide aggregate switching bandwidth of over 1,000 Gb/s. Such routers can accept hundreds of 2.4 to 10 Gb/s line card interfaces. These interfaces are expected to support the most advanced Quality of Service features as well as deliver 99.999% carrier-class availability.

Independent market estimates have placed the deployment of 10 Gb/s line cards at 2 to 4M by 2002. This includes both OC192 Sonet-based transport links as well as 10G Ethernet, which is being targeted first at Metropolitan Area Networks.

A 10 Gb/s interface generates up to 30 M minimum size IP packets per second. Quality of Service processing requires 20 to 30 high-speed memory accesses per packet. Thus each line card must support up to 900 million memory accesses per second. This memory traffic is served traditionally by adding many fast and wide memory components on each line card.

Current OC192 Line Cards are priced in the $100,000 range. This is based upon use of existing discrete solutions to enable early market penetration. This price must come down at least an order of magnitude to support the market growth forecast.

Traditional semiconductor products follow Moore's law which supports a doubling of semiconductor performance every 18 months. Since Internet bandwidth is doubling every six months, this mismatch has resulted in the proliferation of chip count in terabit routers.

There are a number of network system OEM companies considering development of their own 10 Gb/s chips for terabit routers. In addition, several startups are approaching this market. In order to achieve the required memory access speed, the chip sets envisioned by these companies require access to a large amount of high-bandwidth memory.

Typical chipsets using traditional external SRAM and/or SDRAM technology feature high chip counts and very high pin-per-chip counts (typically 1000 pins and above), high power dissipation and EMI generation. Essentially each logic chip is surrounded by a ring of memory devices since a large amount of fast SRAM-class memory is needed per line card (in addition to slower SDRAM memory). In addition to the required SDRAM packet store, approximately 55 chips are needed for a nominally configured 10Gb/s line card- this includes 11 mainly-logic chips plus 44 external state-of-the-art SRAM devices. Total cost for such chipsets will be $10,000 or more. In addition, these chip sets are limited in performance due to their external memory interfaces which are limited to 256 pins or less; at 133 MHz this represents a bandwidth of only 33 Gb/s.

Silicon Access Networks is combining pipeline processor circuit designers, router communications system designers and world-class embedded DRAM circuit designers to prepare a new class of terabit router chipsets based upon smart memories.

These smart memories combine very fast (7.5 ns and below random-access-cycle), very wide (>4096 bits) memories with sophisticated logic based upon proprietary algorithms. For the first time, router system architects have joined with memory circuit architects to specify the exact functions needed at the macro level.

Memory bandwidths up to 1000 Gb/s are available with this smart memory technology.

These smart memories are combined into a terabit router chipset which breaks new ground in price/performance. In addition to the required SDRAM packet store, this chipset will comprise only 11 chips for a nominally configured OC192 line card, including the equivalent of SRAM storage functions- thus saving 44 expensive and power-consuming SRAM devices. Such a chipset will be available for a price well below $4000. This kind of affordability will enable 10G line card pricing to be reduced to $20,000 and thus assure rapid expansion of the Internet infrastructure and once again allow terabit routers to keep up with optical transport links.